1. Field of the Invention
The present invention relates to a semiconductor device, particularly, to the construction and arrangement of a dummy pattern included in a multi-layered wiring structure using, for example, a material having a low relative dielectric constant.
2. Description of the Related Art
FIG. 24 is a plan view showing a semiconductor device having the conventional multi-layered wiring structure. FIG. 25 is a sectional view taken along the line XXV-XXV shown in FIG. 24. As FIGS. 24 and 25 show, a chip ring 103, which is also referred to as a via ring, a crack stopper, a metal ring or a metal fence, is formed in a semiconductor device having a multi-layered wiring structure. The chip ring is composed of stacked structure of plugs 101 and wiring 102 and surrounds a chip. The chip ring 103 is typically formed along a dicing line (scribe line) so as to surround a device region 105. The chip ring serves to prevent the occurrence of cracks in an insulating film caused by mechanical impact in the dicing stage, peeling of the film, and permeation of water or gas into the device region from the side surface in the opening of a dicing line 104. An interlayer insulating film is formed on the dicing line 104 as well as on the device region 105. Also, an opening 106 may be formed in the interlayer insulating film on the dicing line and serve as a mark for the position alignment in, for example, the lithography process. Incidentally, a reference numeral 107 shown in FIG. 24 denotes a functional block.
Also, known is a semiconductor device in which a low dielectric constant material (low-k material) having a relative dielectric constant k smaller than 3 is used for forming the interlayer insulating film in order to decrease the capacitance between the adjacent wirings. In this semiconductor device, it is necessary to use the chip ring 103. A cap film is commonly formed on the low dielectric constant film in order to prevent the semiconductor substrate from being affected by a gas or a chemical solution in the subsequent process steps. Used is a cap film excellent in chemical resistance, of high mechanical strength, and capable of preventing gas or a chemical solution from permeating therethrough.
Sometimes, dust is mixed in the low dielectric constant film during the manufacturing process of the semiconductor device, or small cracks are generated in the low dielectric constant film during, for example, the CMP (chemical mechanical polishing) process. In such a case, a small crack grows into a large one, or the adhesion of the low dielectric constant film 108 is lowered so as to cause the low dielectric constant film 108 to be peeled off as shown in FIG. 26.
Also, if dust or small cracks are present in the low dielectric constant film, the cap film may fail to be formed as desired on each of the low dielectric constant films. In this case, the cap film tends to incur damage in the subsequent process steps. The reliability of the product semiconductor device may be lowered by the permeation of, for example, water from the upper layer of the semiconductor device through the defective portion noted above such as the damaged cap film. Note that the chip ring 103 formed to surround the device region is incapable of coping with the crack occurrence in the low dielectric constant film, with the peeling of the low dielectric constant film, and with the water permeation.
The conventional multi-layered wiring structure gives rise to another problem. In general, water or a process gas tends to be adsorbed on or accumulated in the low dielectric constant film during the manufacturing process of the semiconductor device. The water and the gas bring about problems in the subsequent process steps. For example, the low dielectric constant film may be peeled off. Also, the low dielectric constant film cannot be formed and processed as desired. Further, a good resolution of the pattern cannot be obtained in the low dielectric constant film. In general, the gas undesirably accumulated in the low dielectric constant film is released to the outside through contact holes. Therefore, the gas is not dissipated sufficiently in the portion where the plug density is low, i.e., in the low dielectric constant film with few openings. Problems attributed to the gas are highly likely to arise in this area.
A problem similar to that described above is also generated in the low dielectric constant film 108a in the dicing line 104 during the manufacturing process when water or a process gas permeates from the opening 106 as a mark and enters the low dielectric constant film 108a as shown in FIG. 27. It is conceivable to prevent the diffusion of the water and the gas by inserting a metal film into a region right below the opening 106 as a mark. However, the metal film may be etched because the metal film differs from the insulating film surrounding the metal film in the etching rate. As a result, metal atoms may migrate into the adjacent low dielectric constant film 108, or the accuracy in the position alignment may decrease.